? semiconductor components industries, llc, 2006 february, 2006 ? rev. 8 1 publication order number: cs1124/d cs1124 dual variable?reluctance sensor interface ic the cs1124 is a monolithic integrated circuit designed primarily to condition signals used to monitor rotating parts. the cs1124 is a dual channel device. each channel interfaces to a variable reluctance sensor, and monitors the signal produced when a metal object is moved past that sensor. an output is generated that is a comparison of the input voltage and the voltage produced at the in adj lead. the resulting square?wave is available at the out pin. when the diag pin is high, the reference voltage at in adj is increased. this then requires a larger signal at the input to trip the comparator, and provides for a procedure to test for an open sensor. features ? dual channel capability ? built?in t est mode ? on?chip input voltage clamping ? works from 5.0 v supply ? accurate built?in hysteresis ? pb?free packages are available figure 1. block diagram out1 to p v cc v cc v cc v cc v cc inp1 in adj diag in1 c1 r1 r rs v rs variable reluctance sensor + ? comp1 active clamp v cc v cc inp2 in2 c2 r2 r rs v rs variable reluctance sensor + ? comp2 active clamp out2 to p r adj gnd soic?8 case 751 cs1124 = device code a = assembly location l = wafer lot y = year w = work week = pb?free package marking diagram 1 8 cs112 alyw4 diag gnd 18 out2 in2 out1 in1 v cc in adj see detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ordering information pin connections http://onsemi.com 1 8
cs1124 http://onsemi.com 2 maximum ratings rating value unit storage temperature range ?65 to 150 c ambient operating temperature ?40 to 125 c supply voltage range (continuous) ?0.3 to 7.0 v input voltage range (at any input, r1 = r2 = 22 k) ?250 to 250 v maximum junction temperature 150 c esd susceptibility (human body model) 2.0 kv lead temperature soldering: reflow: (smd styles only) (note 1) 230 peak c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. 60 second maximum above 183 c. electrical characteristics (4.5 v < v cc < 5.5 v, ?40 c < t a < 125 c, v diag = 0; unless otherwise specified.) characteristic test conditions min typ max unit v cc supply operating current supply v cc = 5.0 v ? ? 5.0 ma sensor inputs input threshold ? positive v diag = low v diag = high 135 135 160 160 185 185 mv mv input threshold ? negative v diag = low v diag = high ?185 135 ?160 160 ?135 185 mv mv input bias current (inp1, inp2) v in = 0.336 v ?16 ?11 ?6.0 a input bias current (diag) v diag = 0 v ? ? 1.0 a input bias current factor (k i ) (in adj = inp k i ) v in = 0.336 v, v diag = low v in = 0.336 v, v diag = high ? 152 100 155 ? 157 %inp %inp bias current matching inp1 or inp2 to in adj , v in = 0.336 v ?1.0 0 1.0 a input clamp ? negative i in = ?50 a i in = ?12 ma ?0.5 ?0.5 ?0.25 ?0.30 0 0 v v input clamp ? positive i in = +12 ma 5.0 7.0 9.0 v output low voltage i out = 1.6 ma ? 0.2 0.4 v output high voltage i out = ?1.6 ma v cc ? 0.5 v cc ? 0.2 ? v mode change time delay ? 0 ? 20 s input to output delay i out = 1.0 ma ? 1.0 20 s output rise time c load = 30 pf ? 0.5 2.0 s output fall time c load = 30 pf ? 0.05 2.0 s open?sensor positive threshold v diag = high, r in(adj) = 40 k. note 2 29.4 54 86.9 k logic inputs diag input low threshold ? ? ? 0.2 v cc v diag input high threshold ? 0.7 v cc ? ? v diag input resistance v in = 0.3 v cc , v cc = 5.0 v v in = v cc , v cc = 5.0 v 8.0 8.0 22 22 70 70 k k 2. this parameter is guaranteed by design, but not parametrically tested in production.
cs1124 http://onsemi.com 3 package pin description pin # soic?8 pin symbol function 1 in adj external resistor to ground that sets the trip levels of both channels. functions for both diagnostic and normal mode 2 in1 input to channel 1 3 in2 input to channel 2 4 gnd ground 5 diag diagnostic mode switch. normal mode is low 6 out2 output of channel 2 7 out1 output of channel 1 8 v cc positive 5.0 volt supply input ordering information device package shipping ? cs1124yd8 soic?8 nb 96 units / rail cs1124yd8g soic?8 nb (pb?free) 96 units / rail cs1124ydr8 soic?8 nb 96 units / rail CS1124YDR8G soic?8 nb (pb?free) 96 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. out1 to p v cc v cc v cc v cc v cc inp1 in adj diag in1 c1 r1 r rs v rs variable reluctance sensor + ? comp1 active clamp r adj gnd figure 2. application diagram
cs1124 http://onsemi.com 4 theory of operation normal operation figure 2 shows one channel of the cs1124 along with the necessary external components. both channels share the in adj pin as the negative input to a comparator. a brief description of the components is as follows: v rs ? ideal sinusoidal, ground referenced, sensor output ? amplitude usually increases with frequency, depending on loading. r rs ? source impedance of sensor. r1/r adj ? external resistors for current limiting and biasing. inp1/in adj ? internal current sources that determine trip points via r1/r adj . comp1 ? internal comparator with built?in hysteresis set at 160 mv. out1 ? output 0 v ? 5.0 v square wave with the same frequency as v rs . by inspection, the voltage at the (+) and (?) terminals of comp1 with v rs = 0v are: v + inp1(r1 r rs ) (1) v ? in adj r adj (2) as v rs begins to rise and fall, it will be superimposed on the dc biased voltage at v + . v + inp1(r1 r rs ) v rs (3) to get comparator comp1 to trip, the following condition is needed when crossing in the positive direction, v + v ? v hys (4) (v hys is the built?in hysteresis set to 160 mv), or when crossing in the negative direction, v + v ? v hys (5) combining equations 2, 3, and 4, we get: inp1(r1 r rs ) v rs in adj r adj v hys (6) therefore, v rs(+trp) in adj r adj inp1(r1 r rs ) v hys (7) it should be evident that tripping on the negative side is: v rs(?trp) in adj r adj inp1(r1 r rs ) v hys (8) in normal mode, inp1 in adj (9) we can now re?write equation (7) as: v rs(+tr) inp1(r adj r1 r rs ) v hys (10) by making r adj r1 r rs (11) you can detect signals with as little amplitude as v hys . a design example is given in the applications section. open sensor protection the cs1124 has a diag pin that when pulled high (5.0 v), will increase the in adj current source by roughly 50%. equation (7) shows that a larger v rs(+trp) voltage will be needed to trip comparator comp1. however, if no v rs signal is present, then we can use equations 1, 2, and 4 (equation 5 does not apply in this mode) to get: inp1(r1 r rs ) inp1 k i r adj v hys (12) since r rs is the only unknown variable we can solve for r rs , r rs inp1 k i r adj v hys inp1 r1 (13) equation (13) shows that if the output switches states when entering the diag mode with v rs = 0, the sensor impedance must be greater than the above calculated value. this can be very useful in diagnosing intermittent sensor. input protection as shown in figure 2, an active clamp is provided on each input to limit the voltage on the input pin and prevent substrate current injection. the clamp is specified to handle 12 ma. this puts an upper limit on the amplitude of the sensor output. for example, if r1 = 20 k, then v rs(max) 20 k 12 ma 240 v therefore, the v rs(pk?pk) voltage can be as high as 480 v. the cs1124 will typically run at a frequency up to 1.8 mhz if the input signal does not activate the positive or negative input clamps. frequency performance will be lower when the positive or negative clamps are active. typical performance will be up to a frequency of 680 khz with the clamps active.
cs1124 http://onsemi.com 5 circuit description figure 3 shows the part operating near the minimum input thresholds. as the sin wave input threshold is increased, the low side clamps become active (figure 4). increasing the amplitude further (figure 5 ), the high?side clamp becomes active. these internal clamps allow for voltages up to ?250 v and 250 v on the sensor side of the setup (with r1 = r2 = 22 k) (reference the diagram page 1). figure 6 shows the effect using the diagnostic (diag) function has on the circuit. the input threshold (negative) is switched from a threshold of ?160 mv to +160 mv when diag g oes from a low to a high. there is no hysteresis when diag is high. figure 3. minimum threshold operation in1, 200 mv/div out1, 2.0 v/div 20 ms/div figure 4. low?side clamp in1, 5.0 v/div out1, 2.0 v/div 20 ms/div figure 5. low? and high?side clamps in1, 5.0 v/div out1, 2.0 v/div 20 ms/div figure 6. diagnostic operation diag 5.0 v/div 20 ms/div in1 1.0 v/div out1 5.0 v/div
cs1124 http://onsemi.com 6 application information referring to figure 2, the following will be a design example given these system requirements: r rs 1.5 k ( 12 k is considered open) v rs(max) 120 v pk v rs(min) 250 mv pk f vrs 10 khz @ v rs(min) 40 v pk?pk 1. determine tradeoff between r1 value and power rating. (use 1/2 watt package) p d 120 2
2 r1 1 2w set r1 = 15 k. (the clamp current will then be 120/15 k = 8.0 ma, which is less than the 12 ma limit.) 2. determine r adj set r adj as close to r1 + r rs as possible. therefore, r adj = 17 k. 3. determine v rs(+trp) using equation (7). v rs(+trp) 11 a 17 k 11 a(15 k 1.5 k) 160 m v rs(+trp) 166 mv typical (easily meets 250 mv minimum) 4. calculate worst case v rs(+trp) examination of equation (7) and the spec reveals the worst case trip voltage will occur when: v hys = 180 mv in adj = 16 a inp1 = 15 a r1 = 14.25 k (5% low) r adj = 17.85 k (5% high) v rs(+)max 16 a(17.85 k) 15 a(14.25 k 1.5 k) 180 mv 229 mv which is still less than the 250 mv minimum amplitude of the input. 5. calculate c1 for low pass filtering since the sensor guarantees 40 v pk?pk @ 10 khz, a low pass filter using r1 and c1 can be used to eliminate high frequency noise without affecting system performance. gain reduction 0.29 v 20 v 0.0145 36.7 db therefore, a cut?off frequency, f c , of 145 hz could be used. c1 1 2 f c r1 0.07 f set c1 = 0.047 f. 6. calculate the minimum r rs that will be indicated as an open circuit. (diag = 5.0 v) rearranging equation (7) gives r rs
v hys [inp1 k i r adj ] v rs(+trp) inp1 r1 but, v rs = 0 during this test, so it drops out. using the following as worst case low and high: worst case low (r rs ) worst case high (r rs ) in adj 23.6 a = 15 a 1.57 10.7 a = 7.0 a 1.53 r adj 16.15 k 17.85 k v hys 135 mv 185 mv inp1 16 a 6.0 a r1 15.75 k 14.25 k k i 1.57 1.53 r rs 135 mv 23.6 a 16.15 k 16 a 15.75 k 16.5 k therefore, r rs(min) 16.5 k (meets 12 k system spec) and, r rs(max) 185 mv 10.7 a 17.85 k 6.0 a 14.25 k 48.4 k
cs1124 http://onsemi.com 7 package dimensions soic?8 nb case 751?07 issue ag seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches
scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* package thermal data parameter soic?8nb unit r jc typical 45 c/w r ja typical 165 c/w
cs1124 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 cs1124/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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